Collection of Internet/Collection of Internet.iso/faq/comp/lsi_cad_/part2

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  CIF and Calma layers.  The current CIF output style (see cif ostyle) con-
  trols how Calma stream layers are generated from Magic layers.

  cif [option] [args]

  Read or write files in Caltech Intermediate Form (CIF).

16: CFI (CAD Framework Initiative Inc.)

  (From Randy Kirchhof <[e-mail]>)

              CFI quick FAQ guide for release 1.0, v1.1

  For those of you who may be unfamiliar with our work, The CAD Framework
  Initiative Inc. was formed in May 1988. We're located in Austin, TX,
  although we're a distributed company. We're a  not-for-profit consortium
  formed under the laws of the state of Delaware.  Our mission is to pro-
  vide industry-accepted standards and technology that enable interopera-
  bility of electronic design automation (EDA) applications and data for
  end-users and suppliers world-wide.  This includes interoperability
  between EDA applications as well as the integration of EDA applications
  into CAD frameworks.

  A CAD framework is a software infrastructure which provides a common
  operating environment for CAD tools.  Through a framework, a user should
  be able to launch and manage tools, create, organize, and manage data,
  graphically view the entire design process and perform design management
  tasks such as configuration management, version management, etc.  CFI
  Release 1.0 started shipping in January 1993.

  Q      When can users buy CFI compliant tools?

  A      Eleven vendor companies have announced EDA products and frameworks
         which will be available and compliant with CFI 1.0 standards. CFI
         has initiated a formal certification program for these (and future
         products) as of 12/93. CFI expects to begin awarding the first
         certification brand marks in the first quarter of 1994.  We expect
         to see a rapid expansion of compliant products beginning in the
         third quarter of 1994.

  Q      How can the Standards be obtained?  Are there any restrictions?

  A      The 1.0 Standards, copyrighted by CFI, are available to members
         and non-members priced as a set or individually through CFI Member
         Services [phone].  They will also being distributed under
         license by Cadence, Mentor Graphics, and Viewlogic as part of
         their product documentation.  Versions of the 1.0 Standards are
         available on diskette in an electronic format as well as bound
         manuals.

  Q      How do the CFI Standards relate to vendor framework programs like
         Mentor's Open Door, Viewlogic Power Team and Cadence Connection
         Partners - with so many point tool vendors participating, don't
         they have this problem solved?

  A      The major EDA vendors have been and continue to be challenged by
         their customers over multi-vendor integration.  These programs
         were a practical response by opening up their existing interfaces
         and providing services to assist integration.  CFI 1.0, and future
         releases, will create a functional alternative to a growing subset
         of those interfaces so that the requirement that point tool ven-
         dors create partnership specific versions of their tool will
         decrease.  Actually, the service provided through these programs
         will likely compliment the CFI certification effort as these
         supplier's frameworks become fully certified.

Contact: [e-mail] (CFI Member Services, Jean Gallagher) CFI Main number:
[phone]   Fax: [phone]

17: What synthesis systems are there?

  Thanks to Simon Leung <[e-mail]>, Michel Berkelaar
  <[e-mail]>, Noritake Yonezawa <[e-mail]>, Donald A
  Lobo <[e-mail]>, Greg Ward <[e-mail]>, Peter Duzy,
  Robert Walker <[e-mail]>, Heinrich Kraemer
  <[e-mail]>, Luciano Lavagno <[e-mail]>

  ADPS
  - Case Western Reserve University, USA
  - scheduling and data path allocation
  - Papachristou, C.A. et al.: "A Linear Program Driven Scheduling and
    Allocation Method Followed by an Interconnect Optimization Algorithm",
    Proc. of the 27th DAC, pp. 77-83, June 1990.

  ALPS/LYRA/ARYL
  - Tsing Hua University
  - scheduling and data path allocation
  - Lee, J-H: et al.: "A New Integer Linear Programming Formulation of
    the Scheduling Problem in Data Path Synthesis", Proc. of ICCAD89, pp.
    20-23, November 1989.

  BDSYN
  - University of California, Berkeley, USA
  - FSM synthesis from DECSIM language for multilevel combination-logic
    realization
  - Brayton, R.: "Multiple-level Logic Optimization System",  Proc. of IEEE
    ICCAD, Santa Clara, Nov. 1986

  BECOME
  - AT & T Bell Labs, USA
  - FSM synthesis from C-like language for PLA, PLD and standard cell realization
  - Wei, R-S.: "BECOME: Behavior Level Circuit Synthesis Based on Structure
    Mapping", Proc. of 25th ACM/IEEE Design Automation Conference, pp. 409-414,
    IEEE, 1988

  BOLD
  - logic optimization
  - Bartlett, K. "Synthesis and Optimization of Multilevel Logic Under Timing
    Constraints", IEEE Transactions on Computer-Aided Design, Vol 5, No 10,
    October 1986

  BRIDGE
  - AT & T Bell Labs, USA
  - High-level synthesis FDL2-language descriptions
  - Tseng: "Bridge: A Versatile Behavioral Synthesis System", Proc. of 25th
    ACM/IEEE Design Automation Conference, pp. 415-420, IEEE, 1988

  CADDY
  - Karlsruhe University, Germany
  - behavioral synthesis using VHDL as the input/output language, based on
    data-flow analysis; automated component selection (allocation), scheduling,
    and assignment. Different architechture styles are supported, such as
    multiplexers vs busses and two-phase vs single phase clocks.
  - Camposano, R.: "Synthesing Circuits From Behavioral Descriptions", IEEE
    Transactions on Computer-Aided Design, Vol. 8, No. 2, February 1989
    Rosenstiel, W., Kraemer, H.: "Scheduling and Assignment in High-Level
    Synthesis", in 'High-Level VLSI-Synthesis' R. Camposano, W. Wolf Ed.
    Kluwer, 1991
    Gutberlet P., Mueller J., Kraemer H., Rosenstiel W.: "Automatic Module
    Allocation in High-level Synthesis", Proc. of 1st EURO-DAC, 1992

  CALLAS
  - Siemens, Germany
  - highlevel, algortihmic and logic synthesis (contains CADDY, see
    above)
  - Koster, M. et al.: "ASIC Design Using the High-Level Synthesis
    System CALLAS: A Case Study", Proc. IEEE International Conference on
    Computer Design (ICCD '90), pp. 141-146, Cambridge, Massachusetts,
    Sept. 17-19, 1990

  CAMAD
  - Linkoping University, Sweden
  - scheduling, data path allocation and iteration from a Pascal subset
  - Peng, Z.: "CAMAD: A Unified Data Path/ Control Synthesis
    Environment", Proc. of the IFIP Working Conference on Design
    Methodologies for VLSI and Computer Architecture, pp. 53-67, Sept.
    1988.

  CARLOS
  - Karlsruhe University, Germany
  - multilevel logic optimization for CMOS realizations
  - Mathony, H-J.: "CARLOS: An Automated Multilevel Logic Design System for
    CMOs", IEEE Transactions on Computer-Aided
    Design, Vol 7, No 3, pp. 346-355, March 1988

  CATHEDRAL
  - Univ. of Leuve, Phillips and Siemens, Belgium
  - synthesis of DSP-circuits from algorithm descriptions
  - De Man, H.: "Architecture-Driven Synthesis Techiques for VLSI Implementation
    of DSP Algorithms", Proceedings of the IEEE, Vol. 78, NO. 2, pp. 319,
    February 1990

  CATREE
  - Univ. of Waterloo, Canada
  - scheduling and data path allocation
  - Gebotys, C.H.: "VLSI Design Synthesis with Testability", Proc. of
    the 25th DAC, pp. 16-21, June 1988

  CHARM
  - AT & T Bell Labs., USA
  - data-path synthesis
  - Woo, N-S.: "A Global, Dynamic Register Allocation and Binding for a
    Data Path Synthesis System", Proc. of the 27th DAC, pp. 505-510, June 1990.

  CMU-DA (2)
  - Carnagie-Mellon University, USA
  - behavioral synthesis from ISPS
  - Thomas, D.: "Linking the Behavioral and Structural Domains of Representation
    for Digital System Design", IEEE Transactions on Computer-Aided Design, pp.
    103-110, Vol. 6, No. 1, January 1987

  CONES
  - AT & T Bell Labs, USA
  - FSM synthesis, produces 2-level logic realizations (truth-table)
  - Stroud, C.E.: "CONES: A System for Automated Synthesis of VLSI and
    programmable logic from behavioral models", Proc. of IEEE ICCAD, Santa Clara,
    Nov. 1986.

  DAGAR
  - University of Texas, Austin, USA.
  - scheduling and data-path allocation
  - Raj. V.K.: "DAGAR: An Automatic Pipelined Microarchitecture
    Synthesis System", Proc. of ICCD '89, pp. 428-431, October 1989.

  DELHI
  - IIT
  - design iteration, scheduling and data path allocation
  - Balakrishnan, M. et al.: "Integrated Scheduling and Binding: A
    Synthesis Approach for Design Space Exploration", Proc. of the 26th
    DAC, pp. 68-74, June 1989

  DESIGN AUTOMATION ASSISTANT (DAA)
  - AT & T Bell Labs, USA
  - expert system for data path synthesis
  - Kowalski, T.J. "The VLSI Desig Automation Assistant: An Architecture
    Compiler", Silicon Compilation, pp. 122-152, Addison-Wesley, 1988

  ELF
  - Carleton University, Canada
  - scheduling and data path allocation
  - Girczyc, E.F. et al.: "Applicability of a Subset of Ada as an
    Algorithmic Hardware Description Language for Graph-Based Hardware
    Compilation", IEEE Trans. on CAD, pp. 134-142, April 1985.

  EUCLID
  - Eindhoven University of Technology, Netherlands
  - logic synthesis
  - Berkelaar, Michel R.C.M. and Theeuwen, J.F.M., "Real Area-Powe-Delay
    Trade-off in the EUCLID Logic Synthesis System" , proceedings of the Custom
    Integrated Circuits Conference 1990, Boston MA USA, pp 14.3.1 ff

  EXLOG
  - NEC Corporation, Japan
  - expert system, synthesizes gate level circuits from FDL descriptions
  - M. Watanabe, et al.,: "EXLOG: An Expert System for Logic Synthesis in
    Full-Custom VLSI Design", Proc. of 2nd Int. Conf. Application of Artificial
    Intelligence, August 1987.

  FACE/PISYN
  - General Electric, USA
  - FACE: high-level synthesis tools and a tool framework, PISYN:
    synthesis of pipelined architecture DSP systems (mostly)
  - Smith, W.D. et al.: "FACE Core Environment: The Model and it's
    Application in CAE/CAD Tool Development", Proc. of the 26th DAC, pp.
    466-471, June 1989.

  FLAMEL
  - Stanford University, USA
  - data path and control-logic synthesis from Pascal description
  - Trickey, H. "Flamel: A High-Level Hardware Compiler", IEEE Transactions
    on Computer-Aided Design, Vol 6, No 2, March 1987.

  HAL
  - Carleton University, Canada
  - data path synthesis
  - Paulin, P.: "Force-Directed Scheduling for the Behavioral Synthesis of
    ASIC's", IEEE Transaction on Computer-Aided Design, pp. 661,
    Vol. 8, No. 6, June 1989.

  HARP
  - NTT, Japan
  - scheduling and data path-allocation from FORTRAN
  - Tanaka, T. et al.: "HARP: Fortran to Silicon", IEEE Trans. on CAD,
    pp. 649-660, June 1989.

  HYPER
  - UCB, USA
  - synthesis for realtime applications (scheduling, allocation, module
    binding, controller design)
  - Chu, C-M. et al.: "HYPER: An Interactive Synthesis Environment for
    Real Time Applications", Proc. of ICCD '89, pp. 432-435, October 1989

  IMBSL/RLEXT
  - Univ. of Illinois, USA
  - data-path allocation, RTL-level design
  - Knapp D.W.: "Manual Rescheduling and Incremental Repair of Register
    Level Data Paths", Proc. of ICCAD '89, pp.58-61, November 1989.

  LSS (Logic Synthesis System)
  - IBM, USA
  - logic synthesis and optimization from many RTL-languages
  - Darringer, J. et al. "LSS: A System for Production Logic Synthesis",
    IBM Journal of Research and Developement, vol. 28, No. 5, pp. 272-280,
    Sept 1984.

  MAHA
  - University of Southern California, USA
  - data path synthesis
  - Parker, A.C. "MAHA: A Program for Data Path Synthesis", Proc. 23rd ACM/IEEE
    Design Automation Conference, pp. 252-258, IEEE 1986.

  MIMOLA
  - University of Dortmund, Germany
  - scheduling, data-path allocation and controller design
  - Marwedel, P. "Matching System And Component Behavior in MIMOLA
    Synthesis Tools", Proc. of EDAC '90, pp. 146-156, March 1990.

  OLYMPUS/HERCULES
  - Stanford University, USA
  - behavioral synthesis from C-language (HERCULES), logic and physical
    synthesis
  - De Micheli, G.: "HERCULES - A System for High-Level Synthesis", Proceedings
    of the 25th ACM/IEEE Design Automation Conference, pp. 483-488, IEEE 1988

  SEHWA
  - University of Southern California, USA
  - pipeline-realizations from behavioral descriptions
  - Park, N. "SEWHA: A Program for Synthesis of Pipelines", Proc. 23rd ACM/IEEE
    Design Automation Conference, pp. 454-460, IEEE 1986.

  SIEMENS' SYNTHESIS SYSTEM
  - Siemens, Germany
  - partitioning, data path allocation and scheduling
  - Scheichenzuber, J. et al.: "Global Hardware Synthesis from
    Behavioral Dataflow Descriptions", Proc. of the 27th DAC, pp. 456-461,
    June 1990.

  SIS (formerly MIS (II/MV))
  - University of California, Berkeley, USA
  - synthesis and verification system for sequential logic
  - E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai,
    A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton,
    A. Sangiovanni-Vincentelli: "SIS: A System for Sequential Circuit
    Synthesis", Tech report UCB/ERL M92/41, University of California,
    Berkeley, CA, May 1992

  SOCRATES
  - General Electric, University of Colorado, USA
  - expert system
  - logic optimization and mapping for different technologies
  - de Geus, A.J., "The Socrates Logic Synthesis and Optimization System",
    Design Systems for VLSI Circuits, pp. 473-498, Martinus Nijhoff Publishers,
    1987.

  SPAID
  - Universty of Waterloo, Canada
  - DSP-synthesis for silicon compiler realizations
  - Haroun, B.: "Architectural Synthesis for DSP Silicon Compilers", IEEE
    Transactions on Computer-Aided Design, pp. 431-447, Vol. 8, No 4, April 1989.

  SYNFUL
  - Bell-Northern Research, Canada
  - RTL and FSM synthesis for a production environment
  - G. Ward, "Logic Synthesis at BNR: A SYNFUL Story", Proceedings
    Canadian Conference on Very Large Scale Integration, October 1990.

  SYSTEM ARCHITECT'S WORKBENCH
  - Carnagie-Mellon University, USA
  - behavioral synthesis
  - Thomas, D. "The System Architect's Workbench", Proceedings of the 25th
    ACM/IEEE Design Automation Conference, pp. 337-343, IEEE 1988

  UCB'S SYNTHESIS SYSTEM
  - UCB, USA
  - transformations, scheduling and data path allocation
  - Devadas, S.: "Algorithms for Hardware Allocation in Data Path
    Synthesis", IEEE Trans. on CAD, pp. 768-781, July 89

  SPLICER
  - University of Illinois, USA
  - scheduling and data-path allocation
  - Pangrle, B.M.: "Splicer: A Heuristic Approach to Connectivity
    Binding", Proc. of the 25th DAC, pp. 536-541, June 1988.

  V COMPILER
  - IBM, USA
  - scheduling and data path allocation from V-language
  - Berstis, V: "The V Compiler: Automatic Hardware Design", IEEE Design
    and Test, pp. 8-17, April 1989.

  VSS
  - Univ. of California at Irvine, USA
  - transformations, scheduling and data path allocation from VHDL to
    MILO
  - Lis, J. et al.: "Synthesis from VHDL", Proc. ICCD'88, pp. 378-381,
    October 1988.

  YORKTOWN SILICON COMPILER
  - IBM T.J.Watson Research Centre, USA
  - data path synthesis, logic synthesis etc.
  - Brayton, R.K., et al. "The Yorktown Silicon Compiler", Silicon Compilation,
    pp. 204-311, Addison-Wesley, 1988

18: What free tools are there available, and what can they do?

  (This section can be viewed as a cross reference to the detailed descrip-
  tion of software that follows.)

    Analog VLSI and Neural Systems: Caltech VLSI CAD Tools

    Automated place and route: octtools, Lager

    Digital design environment: Galaxy CAD

    Lsi (polygon) schematic capture: magic, octtools(vem)

    Layout Verification: caltech tools (netcmp), gemini (Washington
    Univerity), wellchk (MUG)

    PCB auto/manual place and route: PADS pcb, PCB (Just for testing lsi
    designs, of course :)

    Simulation: irsim(comes with magic), esim, pspice, isplice3, watand,
    switcap2.Synthesis: octtools, blis, Lager, item, (see section on synthesis)

    Standard schematic capture: PADS logic, PSPICE for windows

19: What Berkeley Tools are available for anonymous ftp?

  available from ic.berkeley.edu:pub

  adore: switched capacitor layout generator.  (Requires Octtools 5.1 to
  compile.)

  bdd:

  road: analog layout router

  sis: simplifies both sum-of-products and generic multi-level boolean
  expressions; it includes many tools including espresso, bdd

  ext2spice: enhanced ext2spice for use with magic

  available from gatekeeper.dec.com:pub/misc

  espresso: simplifies sum-of-products boolean expressions

20: What Berkeley Tools are available through ILP?

  (From MUG 20 Contributed by Carol Block of U. C. Berkeley)

  A new version of the popular circuit simulator, Spice3F2, is now avail-
  able from the Industrial Liaison Program (ILP) Office at the University
  of California, Berkeley.  A new release of Octtools will be forthcoming
  in 1993. Enclosed is a list of software distributed by this office.

  Adore, BBL.2, Berkeley Building-Block Layout System, Berkeley Computer
  Integrated Manufacturing System, Parameter Extraction Program for BSIM,
  Parameter Extraction for BSIM2, Bear-FP, Bert, BLIS, Spice 2G with BSIM
  Implementation, Cider, Ditroff/Gremlin, Ecstasy, EDIF 2 0 0, Elogic,
  ES1:Electrostatis 1-Dimensional Periodic Plasma, Franz Lisp, Glitter,
  IBC: Traveling-Wave-Tube Simulation, IEEE-754 Test Vector, Jsim, Jspice,
  Lanso, Magic-X11R3-Patch, Magic 1990 Decwrl/Livermore Release, Mahjong,
  Mighty, Octtools, Parmex Pix-Parmex, Plasma Device Simulation Codes, PLA
  Tools, Proteus, Ptolemy, Relax, Ritual, Sample, Sample-3D, Additional
  SAMPLE Documentation, Simpl-IPX and Simpl System 5, SIS, SPAM, Sparse,
  Spectre, Spice 2G6, Spice 3F2, Additional SPICE Documentation, Splat,
  Splice 3.0, Supercrystal, SWEC, Tempest, TimberWolf 3.2, Tsize, 1986 VLSI
  Tools, Wombat.

  Within a few weeks, a new catalog will be available via anonymous FTP.
  Users will also be able to obtain forms, ordering instruc- tions and some
  software via this  means.   Generally,  recipients will  have  to com-
  plete an Agreement Form and pay a documentation and handling fee of about
  $250 per program.

  ILP can now distribute most of  its  programs  in  a  variety  of media,
  including: QIC-120, QIC-150, QIC-320, 8mm (2.2 gig), TK 50 (DEC tape for-
  mat), 9-track 1600 bpi and 9-track 6250  bpi.   Visa and  Mastercard ord-
  ers will be accepted on-line by 1993.  Most of the software may be freely
  redistributed either within an organi- zation  or  to other organiza-
  tions, both within the United States and abroad, subject to the certain
  restrictions,  including  all U.S.   Government restrictions, particu-
  larly those concerning ex- port.

  (from blurb+ftp, in the ILP distribution)

  If you have access to ftp, then the tape is free (you just get to suck it
  over by yourself) and you have to remember to print out the docs yourself
  too.  The usual anonymous ftp rules:

          Name:    ic.Berkeley.EDU:edif
          Address:  128.32.132.1

               |-EDIFWorld89.ps
               |-Release_7.6-notes-reversed.ps
               |-Release_7.6-notes.ps
               |-Release_7.6.tar.Z
          edif-|-agreement-reversed.ps
               |-agreement.ps
               |-agreement.tex
               |-assurance-reversed.ps
               |-assurance.ps
               |-assurance.tex
               |-blurb
               |-blurb+ftp

  Other Ports
   -------------------------------------------------------------------- I

  I have a port of the system for SysV, Apollo and HP machines as well
  which is available on request.  Most of these operating systems are
  mature enough now to work directly with Release 7.6.  The system has been
  ported to other non-Unix machines such as VMS, the mac, and various main-
  frame architectures; these latter being a nontrivial effort on the part
  of the individuals involved, but it was accomplished.  I do not have
  these ports; I just know that they are possible because they have been
  performed by others.

          For additional information, contact:

               Industrial Liaison Program
               205 Cory Hall
               Software Distribution Office
               University of California at Berkeley
               Berkeley, CA  94720

               TEL: [phone]
               FAX: [phone]
               [e-mail]

21: Berkeley Spice (Current version 3f4)

  (From spice_info on ic.berkeley.edu)

    Upgrading from Spice 3f2 to 3f4

  The current version is 3f4. This is derived from version 3f2 by applying
  a patch. The patch is available via ftp from ic.berkeley.edu.

    Acquiring Spice 3f2

  For more information on how to acquire Spice3f2, please send your physi-
  cal mailing address to "[e-mail]" and request a software
  catalog.  This will give you all of the necessary information for order-
  ing Spice3f2 and other Berkeley CAD software, including an order form and
  use agreements.  At last check, the cost for spice3f2 was $250.00 (this
  price may change without notice).

    Systems supported and Formats Supplied

      Spice3f2 has been compiled on the following systems:
          Ultrix 4, RISC or VAX
          SunOS 4, Sun3 or Sun4
          AIX V3, RS/6000
          HP-UX 8.0, 9000/700
          MS-DOS on the IBM PC, using MicroSoft C 5.1 or later

  The following systems have been successfully tested either in the past or
  by someone outside of UC Berkeley.

          Dynix 3.0, Sequent Symmetry or Balance (does _not_ take advantage of
                  parallelism)
          HP-UX 7.0, 9000/300
          Irix 3.2, SGI Personal Iris
          NeXT 2.0
          Apple MacIntosh, Using Think C

  Spice3f2 is distributed in source form only.  The C compiler "gcc" has
  been used successfully to compile spice3f2, as well as the standard com-
  pilers for the systems listed above.

  Spice3 displays graphs under X11, PostScript, or a graphics-terminal
  independent library, or as a crude, spice2-like line-printer plot.  On
  the IBM PC, CGA, EGA, and VGA displays are supported through the Micro-
  Soft graphics library.  Note in particular that there is no Suntools
  interface.

  Note the the X11 interface to Spice3 expects realease 4 or later, and
  requires the "Athena Widgets Toolkit" ("Xaw") which may be available only
  in the "unsupported" portion of your vendor software.  A version of
  "OpenWindows" has problems due to undefined routines during linking --
  linking with a null copy of these routines has reportedly worked, but
  "OpenWindows" has not been tested in any way for this release.

  Note that for practical performance a math co-processor is required for
  an IBM PC based on the 286 processor.  A math co-processor is also recom-
  mended for the more advanced IBM PC systems.

  (from posting to comp.lsi.cad) The Windows NT port of spice3e2, Spice32,
  is available via ftp from site
  ftp.cica.indiana.edu:pub/pc/win3/nt/spice100.zip . A similar port of nut-
  meg is included.

  (from Robert Zeff <[e-mail]>)

  Ir Spice32 / Nutmeg32 for Windows NT and
  Win3.1 to Berkeley's version 3F4.  It is available by ftp from
  csustan.csustan.edu:pub/spice/nutmeg.hlp .  I have removed the execut-
  ables for DOD complience.  For access, see the readme file in that direc-
  tory.

  The Unix distribution comes on 1/2" 9-track tape in "tar" format, TK50
  tape (DEC tape), or QIC-150 1/4" cartridge tape (Sun cartridge tape).
  The MS-DOS distribution comes on several 3.5" floppy diskettes (both high
  and low density) in the standard MS-DOS format.  The contents of both
  distributions are identical, including file names.

    New features in 3f2

  The following is a list of new features and fixes from the previous major
  release of Spice3 (3e.2) (see the user's manual for details):

                  AC and DC Sensitivity.
                  MOS3 discontinuity fix ("kappa").
                  Added a new JFET fitting parameter.
                  Minor initial conditions fix.
                  Rewritten or fixed "show" and "trace" commands.
                  New interactive commands "showmod" and "alter".
                  Minor bug-fixes to the Pole-Zero analysis.
                  Miscellaneous bug fixes in the front end.

              Additional features since release 3d.2 are:
                  Lossy transmission line model (not available under MS-DOS).
                  Proper calculation of sheet resistance in MOS models.
                  A new command ("where") to aid in debugging troublesome
                          circuits.
                  Smith-chart plots improved.
                  Arbitrary sources in subcircuits handled correctly.
                  Arbitrary source reciprocal calculations and DC biasing
                          now done correctly.
                  Minor bug-fixes to the Pole-Zero analysis.
                  Miscellaneous bug fixes in the front end.

    A Note on Version Numbering

  Spice versions are numbered "NXM", where "N" is a number representing the
  major release (as in re-write), "X" is a letter representing a feature
  change reflected by a change in the documentation, and "M" is a number
  indicating a minor revision or bug-patch number.

    FTP Access and Upgrades

  There is no anonymous ftp access for the Spice3 source(see below). The
  manual for spice3f2 (in it's postscript format) is available via
  anonymous ftp from ic.berkeley.edu:pub/spice3/um.3f.ps .  If you are
  interested in the troff/me source, contact the email address below (the
  "make" files and whatnot are somewhat cumbersome for the manual).

  Patches or upgrades for Spice3 are _not_ normally supplied, however we
  have made exceptions to this rule, particularly in the case of minor ver-
  sion changes (such as 3f2 to 3f3).

    Email Address for Problems

  Please direct technical inquiries to "[e-mail]" or "spice-
  [e-mail]" (for now these addresses are the same), and ordering
  or redistribution queries to "[e-mail]".  If you find
  that your email to "spice" or "spice-bugs" doesn't get a response in a
  few days, resend your message.

  (from Jim Nance <[e-mail]>)

  Hello all circuits people.  I have uploaded source and binaries for Spice
  2g6 to sunsite.unc.edu:/pub/Linux/Incoming/spice2g6.tar.z .  As you are
  probably aware, spice is a circuit simulator, written at Berkeley.  Ver-
  sion 2g6 was released in 1983.  The current Berkeley version is approxi-
  matly Spice 3f2, however, Berkeley does not want this distributed.
  Source code for Spice 3e2 did escape from Berkeley and was ported to
  Linux (and a lot of other platforms).  This code has been removed from
  anonymous FTP servers, and is therefore no longer available.  Berkeley
  does publish the source code for Spice 2g6.

  I obtained the source code for Spice from a 386BSD ftp site.  The code
  compiled cleanly, with only minor changes to the Makefile being required.
  I also included an ASCII spice manual which I have found helpful.

22: Octtools (Current version 5.1)

  (From the ANNOUNCE-5.1 that comes with it)

  Octtools is a collection of programs and libraries that form an
  integrated system for IC design.  The system includes tools for PLA and
  multiple-level logic synthesis, state assignment, standard-cell, gate-
  matrix and macro-cell placement and routing, custom-cell design, circuit,
  switch and logic-level simulation, and a variety of utility programs for
  manipulating schematic, symbolic, and geometric design data.  Most tools
  are integrated with the Oct data manager and the VEM user interface.

  The software requires UNIX, the window system X11R4 including the Athena
  Widget Set. The design manager VOV and a few other tools require the C++
  compiler g++.

  Octtools-5.1 have been built and tested on the following combinations of
  machines and operating systems: DECstation 3100, 5000 running Ultrix 4.1
  and 4.2; DEC VAX running Ultrix 4.1 and 4.2; Sun 3 and 4 running OS 4.0
  and Sun SparcStation running OS 4.0.  The program has been tried on the
  following machines, but is not supported: Sequent Symmetry, IBM RS/6000
  running AIX 3.1.

  To obtain a copy of Octtools 5.1 (8mm, tk50, or 1/4inch cartridge QIC150)
  and a printed copy of the documentation) for a $250 distribution charge,
  see section on Berkeley ILP.

  Questions may be directed to [e-mail].

23: Ptolemy (Current version 0.5):

  (From comp.lsi.cad)

   What is Ptolemy:
   ---------------

  Ptolemy provides a highly flexible foundation for the specification,
  simulation, and rapid prototyping of systems.  It is an object oriented
  framework within which diverse models of computation can co-exist and
  interact.  For example, using Ptolemy a data-flow system can be easily
  connected to a hardware simulator which in turn may be connected to a
  discrete-event system, etc.  Because of this, Ptolemy can be used to
  model entire systems.

  Ptolemy also has code generation capabilities.  From a flow graph
  description, Ptolemy can generate C code and DSP assembly code for rapid
  prototyping.  Ptolemy can also generate Silage and VHDL descriptions for
  hardware synthesis.

  Ptolemy has been used for a broad range of applications including signal
  processing, telecomunications, parallel processing, wireless communica-
  tions, network design, radio astronomy, real time systems, and
  hardware/software co-design.  Ptolemy has also been used as a lab for
  signal processing and communications courses.  Currently Ptolemy has hun-
  dreds of users in over 100 sites, both in industry and academia.

  Ptolemy is available for the Sun 4 (sparc), DecStation (MIPS), and HP
  (HP-PA) architectures. Installing the system requires 90 Mbytes for
  Ptolemy (more if you optionally remake).  Ptolemy also requires at least
  8 Mbytes of physical memory.

   Getting the New Release:
   -----------------------

  Ptolemy is available via anonymous ftp at: ptolemy.eecs.berkeley.edu This
  site contains the entire Ptolemy distribution, a postscript version of
  the Ptolemy manual, and several Ptolemy papers.

          For those unfamiliar with anonymous ftp, here's what you need to do:
          1.   FTP to Internet host "ptolemy.eecs.berkeley.edu"  (128.32.240.78)
          2.   Login as "anonymous"; use your full email address as the password
          3.   cd pub
          4.   get the README file and follow its instructions.

          Organizations without Internet FTP capability can obtain Ptolemy
          without support from ILP:

                  EECS/ERL Industrial Liaison Program Office
                  Software Distribution
                  205 Cory Hall
                  University of California, Berkeley
                  Berkeley, CA 94720
                  [phone]
                  email: [e-mail]

  This includes printed documentation, including installation instructions,
  a user's guide, and manual pages.  A handling fee (on the order of $250)
  will be charged.

24: Lager (Current version 4.0):

  (From MUG 18)

rized VLSI
  design with a slant towards DSP applications (but not limited to DSP
  applications).  A standard cell library, datapath library, several module
  generators and several pad libraries comprise the cell library.  These
  tools and libraries have originated from UC Berkeley, UCLA, USC, Missis-
  sippi State, and ITD.  The tool development has been funded by DARPA
  under the Rapid Prototyping Contract headed by Bob Brodersen (UC Berke-
  ley).  LAGER 3.0 was described in MUG 15.

  Send email to [e-mail] if you are interested in obtaining
  the toolset via FTP. If you cannot get the distribution via ftp then send
  one 1/4" 600 ft. tape OR an 8 mm tape (Exabyte compatible) to Bob Reese
  by phone at (601)-325-3670 or at one of the following addresses:

          (US Mail Address)
          P.O. Box 6176
          Mississippi State, MS 39762

          (FEDEX)
          2 Research Boulevard
          Starkville, MS 39759

  Be sure to include a return FEDEX waybill we can use to ship your tape
  back to you. Instead of sending a tape and FEDX waybill, you can also
  just send us a check for $75 and we will send you back a tape.  Make the
  check payable to Mississippi State Univ.  The tape will be written on a
  high density tape drive (150 Mb).  Older low density SUN tape drives (60
  Mb) cannot read this format so you need to have access to one of SUN's
  newer tape drives.

25: BLIS (Current version 2.0):

  (From their announcement posted here)

  BLIS (Behavior-to-Logic Interactive Synthesis) is an environment for the
  synthesis of digital circuits from high-level descriptions.  Version 2.0
  supports functional-level synthesis starting from the ELLA hardware
  description language.  Other languages can easily be supported by inter-
  facing a parser to the internal data-flow representation of BLIS.

  BLIS is distributed through the Industrial Liason's Program (ILP) Office
  of the UCB EECS department.  The cost of $250 covers media and distribu-
  tion charges.  Binaries are provided for SUN4 and DEC MIPS architectures
  but BLIS should compile on most other machines supported by the GNU C and
  C++ compilers (e.g. HP, vax, etc).  ELLA language documentation and simu-
  lator are not supplied with the BLIS distribution, but can be obtained
  from Computer General.

26: COSMOS and BDD

  (From their announcement posted here)

                Obtaining and installing COSMOS and BDD.

  The COSMOS package generates switch-level simulators for MOS circuits.
  The BDD package is a subset of COSMOS providing a set of library routines
  for symbolic Boolean manipulation.

  To obtain a copy of either COSMOS or BDD via FTP:

  1. Create an appropriate subdirectory.  For COSMOS, you may want to